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Seoul National University Device Research Laboratory

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Home · Device Optimization of Nano-Plate Transistors for 3.5 nm Technology Node
Home · Device Optimization of Nano-Plate Transistors for 3.5 nm Technology Node

Device Optimization of Nano-Plate Transistors for 3.5 nm Technology Node

저자

Juhyun Kim, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin

저널 정보

Journal of Nanoscience and Nanotechnology

출간연도

2019

링크

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