Abstract:
This paper presents a new model for parasitic extension resistance considering the effect of the spacer dielectric constant on the nanoplate-field-effect transistor (NP-FET) structure. Unlike the previous model that considers the accumulation carriers under the gate overlap, the newly proposed model is developed based on the extension surface potential, which is dependent on the spacer dielectric constant. In addition, surface mobility is redefined by considering the change of the surface electric field with respect to the changes of spacer material. The accuracy of the model was validated by changing physical parameters such as nanoplate width, thickness, source and drain bulk doping concentration, and spacer materials, and it was found that the errors were within 5% of the 3-D technology computer-aided design device simulation results.