컨퍼런스(국내)

Conference
[2016 IVC] Fundamental trade-off between Parasitic Resistance and Capacitance in a Nanowire-FET Tech
[2016 IVC] Design Guideline for 5 nm node Nanowire FET Considering Parasitic Resistance and Capacita
[2016 IVC] Analysis of Work Function Variation and Process Variation effect for 5nm node 3D Stacked
[2016 IVC] Impact of Line Edge Roughness (LER) on Single and Three Stacked Nanowire FET in Ultra-sca
[2016 IVC] Analysis of On Current-boosting and Hot Carrier Degradation Considering Trenched Source/D
[2016 IVC] Analysis on Self Heating Effect on Trench Structure in 5 nm node 3D Stacked Nanowire FET