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[2012 MNE] Patterning of Si nanowire array with electron beam lithography for Sub-22nm Si Nanoelectr
[2012 SNW] 3-D stacked NAND flash memory having lateral bit-line layers and vertical gate
[2012 SNW] Effect of Cu insertion layer between top electrode and switching layer on resistive switc
[2012 SNW] Investigation into the effect of the variation of gate dimensions on program characterist
[2012 AWAD] Novel tunneling field-effect transistor with sigma-shape embedded SiGe sources and reces
[2011 ISDRS] Modulation of Transfer Characteristics of Si Nanowire Tunnel FET on Ultra-Thin-Body and
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