[2009 한국 반도체 학술대회] The modeling of metal layers and vias in RF MOSFET for accurate circuit design

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Home · [2009 한국 반도체 학술대회] The modeling of metal layers and vias in RF MOSFET for accurate circuit design

[2009 한국 반도체 학술대회] The modeling of metal layers and vias in RF MOSFET for accurate circuit design

기간

Feb. 2009

참가자

Jaehong Lee, Yeonam Yoon, Jung Han Choi, Byung-Gook Park, Jong Duk Lee and Hyungcheol Shin

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한국 반도체 학술대회

Jaehong Lee, Yeonam Yoon, Jung Han Choi, Byung-Gook Park, Jong Duk Lee and Hyungcheol Shin, “The modeling of metal layers and vias in RF MOSFET for accurate circuit design,” 한국 반도체 학술대회, Feb. 2009

[2009 한국 반도체 학술대회] The modeling of metal layers and vias in RF MOSFET for accurate circuit design

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