Home · [2016 IVC] Design Guideline for 5 nm node Nanowire FET Considering Parasitic Resistance and Capacita
Home · [2016 IVC] Design Guideline for 5 nm node Nanowire FET Considering Parasitic Resistance and Capacita
[2016 IVC] Design Guideline for 5 nm node Nanowire FET Considering Parasitic Resistance and Capacita
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Jongsu Kim, Hyungwoo Ko, Hyunbae Jeon, Myounggon Kang and Hyungcheol Shin, “Design Guideline for 5 nm node Nanowire FET Considering Parasitic Resistance and Capacitance”, 20th International Vacuum Congress, 2016.