In this paper, the thermal and electrical characteristics of a gate-all-around (GAA) vertical nanoplate-shaped field-effect transistor ( v NPFET) are studied for sub-5-nm technologies using well-calibrated technology computer-aided design simulations. An asymmetric structure of a vertical device has different characteristics that depend on the source/drain position. When the source and the drain are placed at the top and the bottom electrodes, respectively, the GAA- v NPFET drive current increases, but the self-heating effect becomes worse. To co-optimize the performance and the reliability, the gate delay ( τdelay ) and the thermal resistance ( Rth ) were evaluated simultaneously in terms of various geometric factors for the first time, showing that a reckless scaling of the channel thickness below 5 nm significantly degrades the electrothermal characteristics.