In this paper, Self-Heating Effect (SHE) according to depth of STI was analyzed and STI thickness optimization was performed in the plate-shaped vertical field effect transistor (VFET). In case of a VFET, the path of leakage current (I_off) is different from that of a lateral FET (LFET). As a result, I_off of VFET is not influenced by STI depth. For this reason, the STI depth of the VFET is not needed as much as the depth needed to reduce I_off in the LFET. As a result, if the STI depth of the VFET is reduced from 100 nm to 20 nm, which is the drain region depth doped with Arsenic, thermal resistance (R_th) is expected to be reduced by 32.19% and on current (I_on) is expected to be increased by 1.54% without affecting the I_off as compared with STI depth of 100 nm in VFET.