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Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance

저자

Wandong Kim, Jung Hoon Lee, Jang-Gn Yun, Seongjae Cho, Dong Hua Li, Yoon Kim, Doo-Hyun Kim, Gil Sung Lee, Se Hwan Park, Won Bo Shim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park

저널 정보

IEEE Electron Device Letters (EDL)

출간연도

2010

Abstract:

In this letter, a novel SONOS NAND Flash memory array featuring arch-shaped silicon fin and extended word lines (WL) is proposed to improve virtual source/drain (VSD) performance. The arch shape concentrates electric field, resulting in higher electron concentration at the VSD region and higher on -state cell current. In addition, the extended WL process improves the short-channel-effect (SCE) immunity and I – V characteristics. To verify these, an arch VSD NAND array device was fabricated and characterized. The integrated device shows very small SCE while obtaining high on-state cell current. Program and disturbance characteristics of the device are also confirmed.