We proposed for the first time a new double-gate 1T-DRAM cell to be applicable to sub-80-nm DRAM technology that has a silicon-oxide-nitride-oxide-silicon type storage node on the back gate (control gate) for nonvolatile memory (NVM) functionality. An NVM functionality is achieved by Fowler-Nordheim tunneling of electrons into the nitride storage node. Then, holes are accumulated on the back-channel, which makes 1T-DRAM operation in fully depleted silicon-on-insulator (SOI) MOSFETs possible and enhances retention characteristics. We investigated the effect of the NVM functionality on 1T-DRAM performance in nanoscale 1T-DRAM cells through device simulation and verified the effect in 0.6-¿m devices fabricated on SOI wafers.