We extracted final ΔVth , time constant, and activation energy (Ea) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of Vth cumulative probability distribution. As a result, we confirmed that at lower P level, the final ΔVth of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final ΔVth of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger Ea at high P level, whereas the Ea of detrapping mechanism decreases because of barrier lowering effect.