This letter presents the implementation technique to reduce circuit area in designing 2.4 GHz CMOS low-noise amplifier (LNA) using size efficient inductors. We applied a vertically shunt (M6/M5) and a 3-D helical inductor to input and output matching network to obtain low noise figure and to save silicon area, simultaneously. Because these inductors have smaller area occupation, overall Si area was reduced. Moreover, the feedback capacitor, C_f is used to compensate the gain degradation from the high resistive 3-D helical inductor at the LNA output stage. The proposed LNA has a gain of 12.5 dB, noise figure (NF) of 2.72 dB, and −5 dBm IIP3, whereas dissipating 5.3 mA from 1.5 V supply. Without any degradation in terms of circuit performance, the size of proposed LNA is reduced by 49.5% compared with that using the conventional asymmetric inductors. For low cost, the LNA has been fabricated using a 0.18 μm mixed-signal CMOS process with top metal thickness of 0.84 μm.