In this paper, behavior of variation induced by line edge roughness (LER) is investigated for 5 nm node gate-all-around (GAA) nanowire field effect transistors (NWFET) through 3-D technology computer-aided design (TCAD) simulations. The results are compared with 7 nm node FinFET to confirm the influence of LER according to the technology node. We found that LER critically aggravates device performance of a thin layer device by changing the channel thickness. Furthermore, the number of channel deformations induced by the LER plays an important role related with short channel effects (SCEs). Especially, 5 nm node nanowire FET has a very sensitive behavior due to a strong quantum effect (QE) and mobility degradation induced by thin layer, which has two times larger threshold voltage (V _th) variation than that of 7 nm node FinFET.