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Modeling of Grain Boundary Barrier Height for Undoped Polycrystalline Silicon Channel in Macaroni MOSFETs
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Modeling of Grain Boundary Barrier Height for Undoped Polycrystalline Silicon Channel in Macaroni MOSFETs
Modeling of Grain Boundary Barrier Height for Undoped Polycrystalline Silicon Channel in Macaroni MOSFETs
저자
Juhyun Kim, and Hyungcheol Shin
저널 정보
IEEE Transactions on Electron Devices(TED)
출간연도
2022
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Investigation and Modeling of Z-Interference in Poly-Si Channel-Based 3-D NAND Flash Memories
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Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide
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