In this paper, we extracted the parasitic components and proposed a design guideline for 5 nm node nanowire FET using a technology computer-aided design (TCAD) simulation. The research was performed separately on a normal contact structure and recessed contact structure, which can reduce contact resistance. As a result, the parasitic resistance decreased while parasitic capacitance increased as the source/drain electron concentration increased. For intrinsic delay, devices should be designed with high source/drain concentrations in normal contact structures while optimum source/drain concentrations can be found in recessed structures.