The conduction mechanism in Ti/Si ₃ N ₄ /p-Si memory stack is described. In order to analyse the conduction mechanism, we have measured the I–V characteristics in voltage sweep mode and performed I–V curve fitting. The temperature dependence in Ti/Si ₃ N ₄ /p-Si stacked cell has also been investigated because we cannot identify the conduction mechanism just based on the I–V curve fitting. From I–V curve fitting and temperature measurement data, we have found that space charge limited conduction (SCLC) model is the most probable mechanism in both high resistance state (HRS) and low resistance state (LRS).